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CS4353
3.3 V Stereo Audio DAC with 2 VRMS Line Output
Features
Multi-bit Delta-Sigma Modulator 106 dB A-wt Dynamic Range -93 dB THD+N Single-ended Ground Centered Analog Architecture - No DC-blocking Capacitors Required - Integrated Step-up/Inverting Charge Pump - Filtered Line-level Outputs - Selectable 1 or 2 VRMS Full-scale Output Low Clock-jitter Sensitivity Low-latency Digital Filtering Supports Sample Rates up to 192 kHz 24-bit Resolution +3.3 V Charge Pump and Core Logic, +3.3 V Analog, and +0.9 to 3.3 V Interface Power Supplies Low Power Consumption 24-pin QFN, Lead-free Assembly
Description
The CS4353 is a complete stereo digital-to-analog system including digital interpolation, fifth-order multi-bit delta-sigma digital-to-analog conversion, digital de-emphasis, analog filtering, and on-chip 2 VRMS line-level driver from a 3.3 V supply. The advantages of this architecture include ideal differential linearity, no distortion mechanisms due to resistor matching errors, no linearity drift over time and temperature, high tolerance to clock jitter, and a minimal set of external components. The CS4353 is available in a 24-pin QFN package in both Automotive (-40C to +105C) and Commercial (-40C to +85C) grades. The CDB4353 Customer Demonstration Board is also available for device evaluation and implementation suggestions. Please see "Ordering Information" on page 26 for complete details. These features are ideal for cost-sensitive, 2-channel audio systems including video game consoles, DVD players and recorders, A/V receivers, set-top boxes, digital TVs, mini-component systems, and mixing consoles.
Interface Supply (VL) +0.9 V to +3.3 V
Digital Core Logic and Charge Pump Supply (VCP) +3.3 V
Analog Supply (VA) +3.3 V
Reset Level Shifter
Power-On Reset Hardware Control
Step-Up Inverting
+VA_H -VA_H Ground-Centered, 2 Vrms Line Level Outputs
Hardware Control Serial Audio Input
Left Channel PCM Serial Audio Port Auto Speed Mode Detect
Interpolation Filters Multibit Modulator
DAC
Pseudo Diff. Input
Right Channel
Preliminary Product Information
http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2008 (All Rights Reserved)
DEC '08 DS803PP1
CS4353
TABLE OF CONTENTS
1. PIN DESCRIPTIONS ............................................................................................................................ 4 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 6 RECOMMENDED OPERATING CONDITIONS .................................................................................... 6 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 6 DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ) .............................................................. 7 DAC ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ) ............................................................... 8 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE ........................................ 9 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE ........................................................ 10 DIGITAL INTERFACE CHARACTERISTICS ....................................................................................... 11 INTERNAL POWER-ON RESET THRESHOLD VOLTAGES ............................................................. 11 DC ELECTRICAL CHARACTERISTICS .............................................................................................. 12 3. TYPICAL CONNECTION DIAGRAM ................................................................................................... 13 4. APPLICATIONS ................................................................................................................................... 14 4.1.1 Ground-Centered Outputs ..................................................................................................... 14 4.1.2 Full-Scale Output Amplitude Control ..................................................................................... 14 4.1.3 Pseudo-Differential Outputs .................................................................................................. 14 4.8.1 Power-Up Sequences ........................................................................................................... 20 4.8.1.1 External RESET Power-Up Sequence ...................................................................... 20 4.8.1.2 Internal Power-On Reset Power-Up Sequence ......................................................... 20 4.8.2 Power-Down Sequences ....................................................................................................... 20 4.8.2.1 External RESET Power-Down Sequence .................................................................. 20 4.8.2.2 Internal Power-On Reset Power-Down Sequence .................................................... 20 4.9.1 Capacitor Placement ............................................................................................................. 21 5. DIGITAL FILTER RESPONSE PLOTS ................................................................................................. 22 6. PARAMETER DEFINITIONS ................................................................................................................ 24 7. PACKAGE DIMENSIONS .................................................................................................................... 25 8. ORDERING INFORMATION ................................................................................................................ 26 9. REVISION HISTORY ............................................................................................................................ 27
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LIST OF FIGURES
Figure 1.Serial Input Timing ...................................................................................................................... 10 Figure 2.Power-On Reset Threshold Sequence ....................................................................................... 11 Figure 3.Typical Connection Diagram ....................................................................................................... 13 Figure 4.Stereo Pseudo-Differential Output .............................................................................................. 14 Figure 5.IS, up to 24-Bit Data .................................................................................................................. 16 Figure 6.Left-Justified up to 24-Bit Data .................................................................................................... 16 Figure 7.De-Emphasis Curve, Fs = 44.1 kHz ........................................................................................... 17 Figure 8.Internal Power-On Reset Circuit ................................................................................................. 17 Figure 9.Initialization and Power-Down Sequence Diagram ..................................................................... 19 Figure 10.Single-Speed Stopband Rejection ............................................................................................ 22 Figure 11.Single-Speed Transition Band .................................................................................................. 22 Figure 12.Single-Speed Transition Band (detail) ...................................................................................... 22 Figure 13.Single-Speed Passband Ripple ................................................................................................ 22 Figure 14.Double-Speed Stopband Rejection ........................................................................................... 22 Figure 15.Double-Speed Transition Band ................................................................................................. 22 Figure 16.Double-Speed Transition Band (detail) ..................................................................................... 23 Figure 17.Double-Speed Passband Ripple ............................................................................................... 23 Figure 18.Quad-Speed Stopband Rejection ............................................................................................. 23 Figure 19.Quad-Speed Transition Band ................................................................................................... 23 Figure 20.Quad-Speed Transition Band (detail) ....................................................................................... 23 Figure 21.Quad-Speed Passband Ripple ................................................................................................. 23
LIST OF TABLES
Table 1. Power-On Reset Threshold Voltages .......................................................................................... 11 Table 2. Digital I/O Pin Characteristics ..................................................................................................... 12 Table 3. CS4353 Operational Mode Auto-Detect ...................................................................................... 15 Table 4. Single-Speed Mode Standard Frequencies ................................................................................ 15 Table 5. Double-Speed Mode Standard Frequencies ............................................................................... 15 Table 6. Quad-Speed Mode Standard Frequencies ................................................................................. 15 Table 7. Digital Interface Format ............................................................................................................... 16
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CS4353 1. PIN DESCRIPTIONS
1_2VRMS
20
LRCK
IS/LJ
SDIN
24
23
22
21
SCLK MCLK VL DGND FLYPVCP
RESET
19
DEM
1 2 3
18 17 16
VBIAS VA AGND AOUTA AOUT_REF AOUTB
Thermal Pad
4 5
Top-Down (Through Package) View 24-Pin QFN Package
15 14 13
6
7
8
9
10
11
12
VFILT+
FLYN+
FLYP+
Pin Name Pin #
SCLK MCLK VL DGND FLYP+ FLYPVCP VFILT+ FLYN+ FLYNCPGND VFILTAOUTB AOUTA AOUT_REF AGND 1 2 3 4 7 5 6 8 9 11 10 12 13 15 14 16
Pin Description
Serial Clock (Input) - Serial clock for the serial audio interface. Master Clock (Input) - Clock source for the delta-sigma modulator and digital filters. Serial Audio Interface Power (Input) - Positive power for the serial audio interface Digital Ground (Input) - Ground reference for the digital section. Step-Up Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the step-up charge pump's flying capacitor. Charge Pump and Digital Core Logic Power (Input) - Positive power supply for the step-up and inverting charge pumps as well as the digital core logic sections. Step-Up Charge Pump Filter Connection (Output) - Power supply from the step-up charge pump that provides the positive rail for the output amplifiers Inverting Charge Pump Cap Positive/Negative Nodes (Output) - Positive and Negative nodes for the inverting charge pump's flying capacitor. Charge Pump Ground (Input) - Ground reference for the Charge Pump section. Inverting Charge Pump Filter Connection (Output) - Power supply from the inverting charge pump that provides the negative rail for the output amplifiers. Analog Outputs (Output) - The full-scale analog line output level is specified in the Analog Characteristics table. Pseudo Diff. Analog Output Reference (Input) - Ground reference for the analog output amplifiers. This pin must be at the same nominal DC voltage as the AGND pin. Analog Ground (Input) - Ground reference for the low voltage analog section.
4
CPGND
VFILT-
FLYN-
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CS4353
VA VBIAS RESET 17 18 19 Low Voltage Analog Power (Input) - Positive power supply for the analog section. Positive Voltage Reference (Output) - Positive reference voltage for the internal DAC. Reset (Input) - Optional connection for an external reset control. The device enters a powered-down state when this pin is set low (GND) OR when the VCP supply falls below the Voff threshold (see Table 1). This pin should be set high (VL) during normal operation. 1 or 2 VRMS Select (Input) - Selects the analog output full-scale voltage. Setting this pin low (GND) selects 1 VRMS, while setting it high (VL) selects 2 VRMS. De-emphasis (Input) - Selects the standard 50 s/15 s digital de-emphasis filter response for 44.1 kHz sample rates when enabled. Digital Interface Format (Input) - Selects the serial audio interface format. Setting this pin low (GND) selects IS, while setting it high (VL) selects Left-Justified. Left / Right Clock (Input) - Determines which channel, Left or Right, is currently active on the serial audio data line. Serial Audio Data Input (Input) - Input for two's complement serial audio data. Thermal Relief Pad - This pad may be soldered to the board, however it MUST be electrically isolated from all board connections.
1_2VRMS DEM IS/LJ LRCK SDIN Thermal Pad
20 21 22 23 24 -
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CS4353 2. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS
AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. Parameters
DC Power Supply Charge Pump and Digital Core power (Note 1) Low Voltage Analog power (Note 1) Interface power Ambient Operating Temperature (Power Applied) -CNZ -DNZ
Symbol
VCP VA VL TA TA
Min
3.13 3.13 0.85 -40 -40
Typ
3.3 3.3 0.9 to 3.3 -
Max
3.47 3.47 3.47 +85 +105
Units
V V V C C
Notes: 1.
VCP and VA must be supplied with the same nominal voltage. Additional current draw will occur if the supply voltages applied to VCP and VA differ by more than 0.5 V.
ABSOLUTE MAXIMUM RATINGS
AGND = DNGD = CPGND = 0 V; all voltages with respect to ground. Parameters
Charge Pump and Digital Core Logic Power Low Voltage Analog Power Supply Voltage Difference Interface Power Input Current, Any Pin Except Supplies Digital Input Voltage Digital Interface Analog Input Voltage AOUT_REF Ambient Operating Temperature (Power Applied) Storage Temperature DC Power Supply
Symbol
VCP VA |VCP - VA| VL Iin VIN-L VIN-A TA Tstg
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -55 -65
Max
3.63 3.63 0.5 3.63 10 VL+ 0.4 0.5 +125 +150
Units
V V V V mA V V C C
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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CS4353 DAC ANALOG CHARACTERISTICS (COMMERCIAL - CNZ)
Test conditions (unless otherwise specified): TA = 25 C; VCP = VA = 3.3 V; AOUT_REF = AGND = DGND = CPGND = 0 V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. 1_2VRMS = 0 Parameter
Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) (1 kHz) (Notes 4, 5) IOUTmax
1_2VRMS = 1 Min
100 97 1.96 5.54 5 -
Symbol
Min
94 91 0.98 2.77 -
Typ
100 97 92 89 -93 -77 -37 -93 -75 -29 100 115 1.05 2.97 575 0.1 5 100 100 40 -
Max
-87 -71 -31 1.12 3.17 8 1000 0.2
Typ
106 103 98 95 -93 -83 -43 -93 -75 -35 106 115 2.10 5.94 575 0.1 5 100 100 40 -
Max
-87 -77 -37 2.25 6.36 8 1000 0.2
Unit
dB dB dB dB dB dB dB dB dB dB dB dB VRMS Vpp A dB mV ppm/C k pF dB Vpp
Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3)
Total Harmonic Distortion + Noise 24-bit
16-bit
Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation
Analog Output (Note 2)
Full Scale AOUTx Output Voltage Max Current Draw from an AOUTx Pin Interchannel Gain Mismatch Output Offset Gain Drift Output Impedance AC-Load Resistance Load Capacitance AOUT_REF Rejection Analog Reference Input AOUT_REF Input Voltage (Note 8) (Notes 6, 7) ZOUT RL CL AOR
5 -
Notes: 2. Measured between the AOUTx and AOUT_REF pins. 3. One-half LSB of triangular PDF dither is added to data. 4. Measured with the specified minimum AC-Load Resistance present on the AOUTx pins. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. 5. VPP is the controlling specification. VRMS specification valid for sine wave signals only.
Vpp Note that for sine wave signals: VRMS = --------22
6. Measured with AOUT_REF connected directly to ground. Additional impedance between AOUT_REF and ground will lower the AOUT_REF rejection. 7. SDIN = 0. AOUT_REF input test signal is a 60 Hz, 50 mVpp sine wave. Measured by applying the test signal into the AOUT_REF pin and measuring the resulting output amplitude on the AOUTx pin. Specification calculated by: AOR dB = 20 log 10 ---------------------------------------------------------
AOUT_REF AOUT_REF - AOUTx
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CS4353 DAC ANALOG CHARACTERISTICS (AUTOMOTIVE - DNZ)
Test conditions (unless otherwise specified): TA = -40 to +85 C; VCP = VA = 3.13 V to 3.47 V; AOUT_REF = AGND = DGND = CPGND = 0 V; VBIAS, +/-VFILT, and FLYP/N+/- capacitors as shown in Figure 3 on page 13; input test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth 10 Hz to 20 kHz. 1_2VRMS = 0 Parameter
Dynamic Range 24-bit A-Weighted unweighted 16-bit A-Weighted unweighted 0 dB -20 dB -60 dB THD+N 0 dB -20 dB -60 dB (A-wt) (1 kHz) (Notes 4, 5) IOUTmax
1_2VRMS = 1 Min
100 97 1.96 5.54 5 -
Symbol
Min
94 91 0.98 2.77 -
Typ
100 97 92 89 -93 -77 -37 -93 -75 -29 100 115 1.05 2.97 575 0.1 5 100 100 40 -
Max
-87 -71 -31 1.12 3.17 8 1000 0.2
Typ
106 103 98 95 -93 -83 -43 -93 -75 -35 106 115 2.10 5.94 575 0.1 5 100 100 40 -
Max
-87 -77 -37 2.25 6.36 8 1000 0.2
Unit
dB dB dB dB dB dB dB dB dB dB dB dB VRMS Vpp A dB mV ppm/C k pF dB Vpp
Dynamic Performance, Fs = 48, 96, and 192 kHz (Notes 2, 3)
Total Harmonic Distortion + Noise 24-bit
16-bit
Idle Channel Noise / Signal-to-Noise Ratio Interchannel Isolation
Analog Output (Note 2)
Full Scale AOUTx Output Voltage Max Current Draw from an AOUTx Pin Interchannel Gain Mismatch Output Offset Gain Drift Output Impedance AC-Load Resistance Load Capacitance AOUT_REF Rejection Analog Reference Input AOUT_REF Input Voltage (Note 8) (Notes 6, 7) ZOUT RL CL AOR
5 -
8. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output. See Section 4.1.3 for more information.
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CS4353 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE
The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sample rate by multiplying the given characteristic by Fs. Parameter Single-Speed Mode - 48 kHz
Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation De-emphasis Error (Note 11)(Relative to 1 kHz) to -0.01 dB corner to -3 dB corner
Min
0 0 -0.01 0.547 102 0 0 -0.01 .583 80 0 0 -0.01 .635 90 -
Typ
9.4/Fs 4.6/Fs 4.7/Fs
Max
.454 .499 +0.01 0.56/Fs 0 0.14 .430 .499 0.01 0.03/Fs 0 .105 .490 0.01 -
Unit
Fs Fs dB Fs dB s s s dB Fs Fs dB Fs dB s s s Fs Fs dB Fs dB s
(Note 10)
Fs = 44.1 kHz to -0.01 dB corner to -3 dB corner
Double-Speed Mode - 96 kHz
Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) Intra-channel Phase Deviation Inter-channel Phase Deviation
(Note 10)
Quad-Speed Mode - 192 kHz
Passband (Note 9) Frequency Response 10 Hz to 20 kHz StopBand StopBand Attenuation Total Group Delay (Fs = Sample Rate) to -0.01 dB corner to -3 dB corner
(Note 10)
Notes: 9.
Response is clock-dependent and will scale with Fs.
10. For Single- and Double-Speed Mode, the Measurement Bandwidth is from stopband to 3 Fs. For Quad-Speed Mode, the Measurement Bandwidth is from stopband to 1.34 Fs. 11. De-emphasis is available only in Single-Speed Mode. 12. Amplitude vs. Frequency plots of this data are available in "Digital Filter Response Plots" on page 22.
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CS4353 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE
Parameters
MCLK Frequency MCLK Duty Cycle Input Sample Rate (Auto selection) Single-Speed Mode Double-Speed Mode Quad-Speed Mode Fs Fs Fs tsclkl tsclkh Single-Speed Mode Double-Speed Mode Quad-Speed Mode SCLK rising to LRCK edge delay SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time tslrd tslrs tsdlrs tsdh
Symbol
Min
2.048 45 8 84 170 40 20 20 1 --------------------( 128 )Fs 1 -----------------( 64 )Fs 1 -----------------( 64 )Fs 20 20 20 20
Max
51.2 55 54 108 216 60 -
Units
MHz % kHz kHz kHz % ns ns s s s ns ns ns ns
LRCK Duty Cycle SCLK Pulse Width Low SCLK Pulse Width High SCLK Period
LR C K t slrd t slrs t sclkl t sclkh
S C LK t sd lrs S D ATA t sd h
Figure 1. Serial Input Timing
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CS4353 DIGITAL INTERFACE CHARACTERISTICS
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Parameters
High-Level Input Voltage Low-Level Input Voltage Input Leakage Current Input Capacitance 1.2 V < VL 3.3 V 0.9 V VL 1.2 V 1.2 V < VL 3.3 V 0.9 V VL 1.2 V
Symbol
VIH VIH VIL VIL Iin
Min
0.7xVL 0.9xVL -
Typ
8
Max
0.3xVL 0.1xVL 10 -
Units
V V V V A pF
INTERNAL POWER-ON RESET THRESHOLD VOLTAGES
Test conditions (unless otherwise specified): AGND = DGND = CPGND = 0 V; all voltages with respect to ground. Parameters
Internal Reset Asserted at Power-On Internal Reset Released at Power-On Internal Reset Asserted at Power-Off
Symbol
Von1 Von2 Voff
Min -
Typ 1.00 2.14 2.00
Max -
Units V V V
Table 1. Power-On Reset Threshold Voltages
VCP
Von2 Von1
DGND
Voff
reset
(internal)
HI
LO
reset No Power undefined
reset active
DAC Ready
reset active
Figure 2. Power-On Reset Threshold Sequence
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CS4353 DC ELECTRICAL CHARACTERISTICS
Test conditions (unless otherwise specified): VCP = VA = VL = 3.3 V; AGND = DGND = CPGND = 0 V; SDIN = 0; all voltages with respect to ground. Parameters Power Supplies
Power Supply Current (Note 13) Normal Operation IVCP IVA IVL IPD 36 2.4 0.1 65 127 1 60 60 3.3 6.6 6.6 6.6 2.1 43 3 0.2 152 mA mA mA A mW mW dB dB V V V V V
Symbol
Min
Typ
Max
Units
Power-Down, All Supplies (Note 14) Power Dissipation (All Supplies) Normal Operation, 1_2VRMS = 0 (Note 13) Power-Down (Note 14) Power Supply Rejection Ratio (Note 15) (1 kHz) (60 Hz)
PSRR
DC Output Voltages
Pin Voltage FLYP+ to FLYPVFILT+ to GND (Note 16) FLYN+ to FLYNGND to VFILT- (Note 16) VA to VBIAS
Notes: 13. Current consumption increases with increasing sample rate and increasing MCLK frequency. Typical values are based on Fs = 48 kHz and MCLK = 12.288 MHz. Maximum values are based on highest sample rate and highest MCLK frequency; see Switching Specifications - Serial Audio Interface. Variance between speed modes is small. 14. Power-down is defined as RESET pin = Low with all clock and data lines held static low. All digital inputs have a weak pull-down (approximately 50 k) which is only present during reset. Opposing this pulldown will slightly increase the power-down current. 15. Valid with the recommended capacitor value on VBIAS as shown in the typical connection diagram in Section 3. 16. Typical voltage shown for "Initialization State", see Section 4.7. Typical voltage may be up to 1.5 V lower during normal operation.
2.1
Digital I/O Pin Characteristics
Input and output levels and associated power supply voltage are shown in Table 2. Logic levels should not exceed the corresponding power supply voltage.
Pin Name RESET MCLK LRCK SCLK SDIN DEM IS/LJ 1_2VRMS Power Supply I/O Input Input Input Input Input Input Input Input Driver Receiver 0.9 V - 3.3 V, with Hysteresis 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V 0.9 V - 3.3 V
VL
Table 2. Digital I/O Pin Characteristics
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CS4353 3. TYPICAL CONNECTION DIAGRAM
+3.3 V
2.2 F
+
0.1 F
0.1 F
+
6 17
2.2 F
VC P
VA
VBIAS +VFILT
18
8
2
MCLK SCLK LRCK FLYP5
0.1 F
+
2.2 F
Digital Audio Processor
1
FLYP+
7
+
23
2.2 F
24
SDIN
Line Level Out Left & Right
562 2.2 nF
Rext
CS4353
+0.9 V to +3.3 V
0.1 F
3
AOUTA
15
VL
AOUT_REF AOUTB
14
Note 2 RESET IS/LJ
2.2 nF
13
Rext
562
9
Note 1
19
FLYN+ FLYN-
+
11
Hardware Control
22
2.2 F
21
DEM 1_2VRMS
-VFILT
12
Note 1: Values shown are for Fc = 130 kHz. Capacitors must be C0G or equivalent.
20
0.1 F
+
22 F
Note 2:Connect RESET to VL if internal power-on reset is used.
D
G ND
PG N
C
10
D
4
Figure 3. Typical Connection Diagram
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16
N D
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CS4353 4. APPLICATIONS
4.1 4.1.1 Line Outputs Ground-Centered Outputs
An on-chip charge pump creates both positive and negative high-voltage supplies, which allows the fullscale output swing to be centered around ground. This eliminates the need for large DC-blocking capacitors which create audible pops at power-on, allows the CS4353 to deliver a larger full-scale output at lower supply voltages, and provides improved bandwidth frequency response.
4.1.2
Full-Scale Output Amplitude Control
The full-scale output voltage amplitude is selected via the 1_2VRMS pin. When the pin is connected to VL, the full-scale output voltage at the AOUTx pins is approximately 2 VRMS. When the pin is connected to GND, the full-scale output voltage at the AOUTx pins is approximately 1 VRMS. Additional impedance between the AOUTx pin and the load will lower the voltage delivered to the load. See the DAC Analog Characteristics (Commercial - CNZ) or DAC Analog Characteristics (Automotive - DNZ) table for the complete specifications of the full-scale output voltage.
4.1.3
Pseudo-Differential Outputs
The CS4353 implements a pseudo-differential output stage. The AOUT_REF input is intended to be used as a pseudo-differential reference signal. This feature provides common mode noise rejection with singleended signals. Figure 4 shows a basic diagram outlining the internal implementation of the pseudo-differential output stage, including a recommended stereo pseudo-differential output topology. If pseudo-differential output functionality is not required, simply connect the AOUT_REF pin to ground next to the CS4353. If a split-ground design is used, the AOUT_REF pin should be connected to AGND. See the Absolute Maximum Ratings table for the maximum allowable voltage on the AOUT_REF pin. Applying a DC voltage on the AOUT_REF pin will cause a DC offset on the DAC output.
Internal Left DAC Signal AOUTA
// // //
Left Output
(pseudo-differential traces)
AOUT_REF
GND
(pseudo-differential traces)
AOUTB Internal Right DAC Signal
Right Output
Psuedo-differential output improves common mode rejection, reducing external system noise
Figure 4. Stereo Pseudo-Differential Output
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4.2 Sample Rate Range/Operational Mode Detect
The CS4353 operates in one of three operational modes. The device will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK frequency, falls within one of the ranges illustrated in Table 3. Sample rates outside the specified range for each mode are not supported. In addition to a valid LRCK frequency, a valid serial clock (SCLK) and master clock (MCLK) must also be applied to the device for speed mode auto-detection; see Figure 9. Input Sample Rate (Fs)
8 kHz - 54 kHz 84 kHz - 108 kHz 170 kHz - 216 kHz
Mode
Single-Speed Mode Double-Speed Mode Quad-Speed Mode
Table 3. CS4353 Operational Mode Auto-Detect
4.3
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks. The left/right clock, defined also as the input sample rate (Fs), must be synchronously derived from the MCLK signal according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard audio sample rates and the required MCLK frequency, are illustrated in Tables 4-6. Refer to Section 4.4 for the required SCLK timing associated with the selected Digital Interface Format and to "Switching Specifications - Serial Audio Interface" on page 10 for the maximum allowed clock frequencies.
Sample Rate (kHz)
32 44.1 48
256x
8.1920 11.2896 12.2880
384x
12.2880 16.9344 18.4320
MCLK (MHz) 512x
16.3840 22.5792 24.5760
768x
24.5760 33.8688 36.8640
1024x
32.7680 45.1584 49.1520
Table 4. Single-Speed Mode Standard Frequencies
Sample Rate (kHz)
88.2 96
128x
11.2896 12.2880
192x
16.9344 18.4320
MCLK (MHz) 256x
22.5792 24.5760
384x
33.8688 36.8640
512x
45.1584 49.1520
Table 5. Double-Speed Mode Standard Frequencies
Sample Rate (kHz)
176.4 192
128x
22.5792 24.5760
MCLK (MHz) 192x
33.8688 36.8640
256x
45.1584 49.1520
Table 6. Quad-Speed Mode Standard Frequencies
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CS4353
4.4 Digital Interface Format
The device will accept audio samples in either IS or Left-Justified digital interface formats, as illustrated in Table 7. The desired format is selected via the IS/LJ pin. For an illustration of the required relationship between the LRCK, SCLK and SDIN, see Figures 5-6. For all formats, SDIN is valid on the rising edge of SCLK. Also, SCLK must have at least 32 cycles per LRCK period in the Left-Justified format. For more information about serial audio formats, refer to Cirrus Logic Application Note AN282: The 2-Channel Serial Audio Interface: A Tutorial, available at http://www.cirrus.com.
IS/LJ
0 1
Description IS, up to 24-bit Data Left-Justified, up to 24-bit Data
Table 7. Digital Interface Format
Figure
5 6
LR CK
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
S D IN
M SB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LSB
Figure 5. IS, up to 24-Bit Data
LR C K
L e ft C h a n n e l
R ig h t C h a n n e l
SCLK
S D IN
MSB
-1 -2 -3 -4 -5
+5 +4 +3 +2 +1
LSB
M SB
-1 -2 -3 -4
+5 +4 +3 +2 +1
LS B
Figure 6. Left-Justified up to 24-Bit Data
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4.5 De-Emphasis Control
The device includes on-chip digital de-emphasis. Figure 7 shows the de-emphasis curve for Fs equal to 44.1 kHz. The frequency response of the de-emphasis curve scales with changes in the sample rate, Fs. The de-emphasis error will increase for sample rates other than 44.1 kHz. When the DEM pin is connected to VL, the 44.1 kHz de-emphasis filter is activated. When the DEM pin is connected to GND, the de-emphasis filter is turned off.
Gain dB T1=50 s 0dB
T2 = 15 s
-10dB
F1 3.183 kHz
F2 Frequency 10.61 kHz
Figure 7. De-Emphasis Curve, Fs = 44.1 kHz
Note:
De-emphasis is only available in Single-Speed Mode.
4.6
Internal Power-On Reset
The CS4353 features an internal power-on reset (POR) circuit. The POR circuit allows the RESET pin to be connected to VL during power-up and power-down sequences if the external reset function is not needed. This circuit monitors the VCP supply and automatically asserts or releases an internal reset of the DAC's digital circuitry when the supply reaches defined thresholds (see "Internal Power-On Reset Threshold Voltages" on page 11). No external clocks are required for the POR circuit to function.
VCP Power-On Reset Circuit DGND reset (internal) RESET (external)
Figure 8. Internal Power-On Reset Circuit When power is first applied, the POR circuit monitors the VCP supply voltage to determine when it reaches a defined threshold, Von1. At this time, the POR circuit asserts the internal reset low, resetting all of the digital circuitry. Once the VCP supply reaches the secondary threshold, Von2, the POR circuit releases the internal reset.
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Note: For correct operation of the internal POR circuit, the voltage on VL must rise before or simultaneously with VCP.
When power is removed and the VCP voltage reaches a defined threshold, Voff, the POR circuit asserts the internal reset low, resetting all of the digital circuitry.
4.7
Initialization
When power is first applied, the DAC enters a reset (low power) state at the beginning of the initialization sequence. In this state, the AOUTx pins are weakly pulled to ground and VBIAS is connected to VA. The device will remain in the reset state until the RESET pin is brought high. Once the RESET pin is high, the internal digital circuitry is reset and the DAC enters a power-down state until MCLK is applied. Alternatively, if no external reset control is required, the internal power-on reset can be used by tying the RESET pin to VL (see Section 4.6). Once MCLK is valid, the device enters an initialization state in which the charge pump powers up and charges the capacitors for both the positive and negative high-voltage supplies. Once LRCK and SCLK are valid, the number of MCLK cycles is counted relative to the LRCK period to determine the MCLK/LRCK frequency ratio. Next, the device enters the power-up state in which the interpolation and decimation filters and delta-sigma modulators are turned on, the internal voltage reference, VBIAS, powers up to normal operation, the analog output pull-down resistors are removed, and power is applied to the output amplifiers. After this power-up state sequence is complete, normal operation begins and analog output is generated. If valid MCLK, LRCK, and SCLK are applied to the DAC before RESET is set high, the total time from RESET being set high to the analog audio output from AOUTx is less than 50 ms. See Figure 9 for a diagram of the device's states and transition conditions.
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USER: Apply Power USER: RESET Set Low or Remove MCLK
Reset State
Outputs Grounded
USER: RESET Set High or RESET Tied High (if using POR)
Power-Down State
USER: Apply MCLK
Initialization State
USER: Apply LRCK and SCLK
MCLK/LRCK Ratio Detection
USER: Change MCLK/LRCK ratio
Valid MCLK/LRCK Ratio
Power-Up State
Outputs Muted
Normal Operation State
Analog Output Generated
Valid MCLK/LRCK Ratio
USER: Change MCLK/LRCK ratio
Mute State
Figure 9. Initialization and Power-Down Sequence Diagram
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4.8 4.8.1 Recommended Power-Up and Power-Down Sequences Power-Up Sequences 4.8.1.1 External RESET Power-Up Sequence
Follow the power-up sequence below if the external RESET pin is used: 1. Hold RESET low while the power supplies are turned on. 2. Set the IS/LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. Provide the correct MCLK, LRCK, and SCLK signals locked to the appropriate frequencies as discussed in Section 4.3. 4. After the power supplies, configuration pins, and clock signals are stable, bring RESET high. The device will initiate the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from AOUTx within 50 ms after RESET is set high.
4.8.1.2
Internal Power-On Reset Power-Up Sequence
Follow the power-up sequence below if the internal power-on reset is used: 1. Hold RESET high (connected to VL) while the power supplies are turned on. The power-on reset circuitry will function as described in Section 4.6. 2. Set the IS/LJ, 1_2VRMS, and DEM configuration pins to the desired state. 3. After the power supplies and configuration pins are stable, provide the correct MCLK, LRCK, and SCLK signals to progress from the `Power-Down State' in the power-up sequence seen in Figure 9. The sequence will complete and audio will be output from the AOUTx pins within 50 ms after valid clocks are applied.
4.8.2
Power-Down Sequences 4.8.2.1 External RESET Power-Down Sequence
Follow the power-down sequence below if the external RESET pin is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. Bring RESET low. 3. Remove the power supply voltages.
4.8.2.2
Internal Power-On Reset Power-Down Sequence
Follow the power-down sequence below if the internal power-on reset is used: 1. For minimal pops, set the input digital data to zero for at least 8192 consecutive samples. 2. Remove the MCLK signal without applying any glitched pulses to the MCLK pin. 3. Remove the power supply voltages. Note: A glitched pulse is any pulse that is shorter than the period defined by the minimum/maximum MCLK signal duty cycle specification and the nominal frequency of the input MCLK signal. A transient may occur on the analog outputs if the MCLK signal duty cycle specification is violated when the MCLK signal is removed during normal operation; see "Switching Specifications - Serial Audio Interface" on page 10.
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4.9 Grounding and Power Supply Arrangements
As with any high-resolution converter, the CS4353 requires careful attention to power supply and grounding arrangements if its potential performance is to be realized. Figure 3 shows the recommended power arrangements, with VCP, VA, and VL connected to clean supplies. It is strongly recommended that a single ground plane be used, with the DGND, CPGND, and AGND pins all connected to this common plane. Should it be necessary to split the ground planes, the DGND and CPGND pins should be connected to the digital ground plane and the AGND pin should be connected to the analog ground plane. In this configuration, it is critical that the digital and analog ground planes be tied together with a low-impedance connection, ideally a strip of copper on the printed circuit board, at a single point near the CS4353. All signals, especially clocks, should be kept away from the VBIAS pin in order to avoid unwanted coupling into the DAC.
4.9.1
Capacitor Placement
Decoupling capacitors should be placed as close to the device as possible, with the low-value ceramic capacitor being the closest. To further minimize impedance, these capacitors should be located on the same PCB layer as the device. If desired, all supply pins may be connected to the same supply, but a decoupling capacitor should still be placed on each supply pin. See DC Electrical Characteristics for the voltage present across pin pairs. This is useful for choosing appropriate capacitor voltage ratings and orientation if electrolytic capacitors are used. The CDB4353 evaluation board demonstrates the optimum layout and power supply arrangements.
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CS4353 5. DIGITAL FILTER RESPONSE PLOTS
0 0
-20
-20
Amplitude (dB)
Amplitude (dB)
-40
-40
-60
-60
-80
-80
-100
-100
-120 0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
-120 0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 10. Single-Speed Stopband Rejection
Figure 11. Single-Speed Transition Band
0
0.02
-1
0.015
-2 0.01 -3 0.005
Amplitude (dB)
Amplitude (dB)
-4
-5
0
-6
-0.005
-7 -0.01 -8 -0.015
-9
-10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
-0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 12. Single-Speed Transition Band (detail)
Figure 13. Single-Speed Passband Ripple
0
0
20
20
Amplitude (dB)
Amplitude (dB)
40
40
60
60
80
80
100
100
120
120
0.4
0.5
0.6 0.7 0.8 Frequency(normalized to Fs)
0.9
1
0.4
0.42
0.44
0.46
0.48 0.5 0.52 Frequency(normalized to Fs)
0.54
0.56
0.58
0.6
Figure 14. Double-Speed Stopband Rejection
Figure 15. Double-Speed Transition Band
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0
0.02
1
0.015
2
0.01
3
Amplitude (dB)
5
Amplitude (dB)
4
0.005
0
6
0.005
7
0.01
8
9
0.015
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0.02
0
0.05
0.1
0.15
0.2 0.25 0.3 Frequency(normalized to Fs)
0.35
0.4
0.45
0.5
Figure 16. Double-Speed Transition Band (detail)
Figure 17. Double-Speed Passband Ripple
0
0
20
20
40 Amplitude (dB)
Amplitude (dB)
40
60
60
80
80
100
100
120
120
0.2
0.3
0.4
0.5 0.6 0.7 Frequency(normalized to Fs)
0.8
0.9
1
0.2
0.3
0.4 0.5 0.6 Frequency(normalized to Fs)
0.7
0.8
Figure 18. Quad-Speed Stopband Rejection
0
0.2
Figure 19. Quad-Speed Transition Band
1
0.15
2
0.1
3
0.05
Amplitude (dB)
Amplitude (dB)
0.05 0.1 0.15 0.2
4
5
0
6
7
8
9
10 0.45
0.46
0.47
0.48
0.49 0.5 0.51 Frequency(normalized to Fs)
0.52
0.53
0.54
0.55
0
0.05
0.1 0.15 Frequency(normalized to Fs)
0.2
0.25
Figure 20. Quad-Speed Transition Band (detail)
Figure 21. Quad-Speed Passband Ripple
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CS4353 6. PARAMETER DEFINITIONS
Total Harmonic Distortion + Noise (THD+N) The ratio of the RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth (typically 10 Hz to 20 kHz), including distortion components. Expressed in decibels. Dynamic Range The ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with a -60 dBFS signal. 60 dB is then added to the resulting measurement to refer the measurement to full scale. This technique ensures that the distortion components are below the noise level and do not affect the measurement. This measurement technique has been accepted by the Audio Engineering Society, AES171991, and the Electronic Industries Association of Japan, EIAJ CP-307. Interchannel Isolation A measure of crosstalk between the left and right channels. Measured for each channel at the converter's output with all zeros to the input under test and a full-scale signal applied to the other channel. Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/C.
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CS4353 7. PACKAGE DIMENSIONS 24L QFN (4.00 mm BODY) PACKAGE DRAWING
D
1.00 REF
b
e PIN #1 CORNER
1.00 REF
PIN #1 IDENTIFIER LASER MARKING
E
E2
A1 A D2 L
TOP VIEW
SIDE VIEW
BOTTOM VIEW
DIM
A A1 b e D D2 E E2 L
MIN
0.00000 0.00787 0.01772 0.10433 0.10433 0.01181
INCHES NOM
MAX
MIN
MILLIMETERS NOM
0.25 0.50 4.00 BSC 2.70 4.00 BSC 2.70 0.40
NOTE MAX
1.00 0.05 0.30 0.55 2.75 2.75 0.50 1 1 1, 2 1 1 1 1 1 1
0.03937 0.00197 0.00 0.00984 0.01181 0.20 0.01969 0.02165 0.45 0.15748 BSC 0.10630 0.10827 2.65 0.15748 BSC 0.10630 0.10827 2.65 0.01575 0.01969 0.30 Controlling Dimension is Millimeters
Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1994. 2. Dimensioning lead width applies to the metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip.
Parameter
Junction to Ambient Thermal Impedance 2 Layer Board 4 Layer Board
Symbol
JA JA
Min
-
Typ
68 28
Max
-
Units
C/Watt C/Watt
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CS4353 8. ORDERING INFORMATION
Product CS4353 CS4353 CDB4353 Description Package Pb-Free 3.3 V Stereo Audio DAC 24-pin QFN YES with 2 VRMS Line Output 3.3 V Stereo Audio DAC 24-pin QFN with 2 VRMS Line Output CS4353 Evaluation Board YES Container Rail Commercial -40 to +85 C Tape & Reel Rail Automotive -40 to +105 C Tape & Reel Grade Temp Range Order # CS4353-CNZ CS4353-CNZR CS4353-DNZ CS4353-DNZR CDB4353
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CS4353 9. REVISION HISTORY
Release Changes
- Updated interchannel isolation specification in the DAC Analog Characteristics (Commercial - CNZ) and DAC Analog Characteristics (Automotive - DNZ) specification tables. - Updated minimum Quad-Speed Mode SCLK period in the Switching Specifications - Serial Audio Interface table. - Updated power supply current and power dissipation specifications in the DC Electrical Characteristics table. - Updated the FLYN+ to FLYN- DC voltage in the DC Electrical Characteristics table. - Added "SDIN = 0" to the test conditions in the DC Electrical Characteristics table. - Updated Section 4.8.1.1 on page 20. - Updated output impedance specification in the DAC Analog Characteristics (Commercial - CNZ) and DAC Analog Characteristics (Automotive - DNZ) specification tables.
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Contacting Cirrus Logic Support
For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find one nearest you, go to www.cirrus.com.
IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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